Method and apparatus to optimize an integrated circuit design using transistor folding

ABSTRACT

A method and system are disclosed to optimize an integrated circuit layout design by determining possible lengths of layout rows that will reduce the total area of the integrated circuit layout (FIG.  4 B). The possible row lengths ( 401 B) are determined and stored in a memory unit as a set of possible optimal row length values. A set of possible optimal row heights corresponding to the determined set of possible rowlengths is determined and the total chip area is iteratively calculated. Optimal values of rowlength and row height are chosen based upon the maximum chip area reduction. Once the optimal row length and height parameters are chosen, transistor devices placed in each row of the integrated circuit layout are folded to achieve the optimal row length and height.

1. TECHNICAL FIELD

[0001] The invention relates to a system and method of optimizingintegrated circuits (ICs), and in particular to a system and method forproviding an optimal IC layout designs using transistor folding.

2. BACKGROUND

[0002] As designers strive to improve the capabilities of new ICs,minimization of IC size continues to be an underlying goal. Typically,IC designs utilize previously developed circuit designs, from a libraryof circuit designs in new combinations and configurations to createwholly new designs capable of performing new functions or perhapsoptimizing the performance of the previous IC designs. While someindividual IC designs have been optimized in terms of performance andsize, the combination of these circuits with other circuits into newcustom designed ICs often utilize a re-configuration of transistorgeometry to provide the optimal design of the overall new customdesigned IC.

[0003] When custom designing a new high performance IC, individualtransistors may be tuned to provide optimal speed. However, manuallytuning individual transistor is both tedious and error-prone. While someautomated transistor sizing tools exist to optimize individualtransistors, the individual transistors still benefit from an optimalphysical layout design to provide an optimal IC. Conventional layoutdesigns place individual transistors on a layout using a row-baseddesign style. In most cases, conventional row-based layout designsresult in an inefficient utilization of chip area because the individualtransistors are of non-uniform size and shape.

[0004] Transistor folding is a method of re-configuring the geometry ofa known transistor design in order to minimize total chip area, whileretaining the performance characteristics of the known design. In customIC physical layout design, high performance requirements of new circuitdesigns nay necessitate the integration of various transistor devices ofdifferent sizes. In the typical row-based layout design style,non-uniform transistor heights in a row tend to waste overall IC chiparea. Therefore, it is highly desirable to provide a system and methodof transistor device folding which takes advantage of the differentrows' lengths to achieve efficient area utilization of the entire IClayout.

3. SUMMARY

[0005] Accordingly, the present invention seeks to provide an IC designwith an optimal chip area. An embodiment of the present invention isdirected to a system and method of chip area optimization usingrow-based transistor folding techniques with a global impact analysis.By analyzing each transistor device placed in an IC layout, theembodiment may determine how best to re-configure the geometry ofindividual transistor, through the use of transistor folding, in orderto optimize the size of the overall IC. The chip area that is optimizedmay consist of both the transistor area and the routing area. Anotherembodiment provides for sizing optimization in two dimensions. Moreover,another embodiment further analyzes the electrical impact transistorfolding will have on each device placed within the IC layout. Theembodiment utilizes this analysis to provide adequate routing areabetween rows to reduce parasitic electrical effects in its optimizationprocess. Still further, another embodiment provides IC sizingoptimization in a time that is linearly related to the overall number oftransistors integrated within a single device. The transistor foldingtechniques of the various disclosed embodiments in conjunction withtransistor sizing are designed to optimize the IC at the layout stage.

[0006] 4. BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is a diagram of a computer system that may be used inconnection with various embodiments of the invention as describedherein;

[0008]FIG. 2 is a diagram of a simplified integrated circuit as may berepresented in the form of a virtual component block;

[0009]FIG. 3 is a diagram of a general process flow for a circuitdesign, illustrating various levels of circuit abstraction;

[0010]FIGS. 4a and 4 b illustrate the principle of transistor folding;

[0011]FIG. 5 illustrates an example of a physical layout aftertransistor sizing;

[0012]FIG. 6 illustrates an example of the optimized physical layoutafter transistor folding.

5. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Preferred embodiments will now be described, with reference asnecessary to the accompanying drawings.

[0014] Systems and methods are disclosed for physical layout of ICs inwhich transistors are folded in a manner to achieve efficient componentlayout by taking advantage of differences in the lengths of differentrows in the circuit layout. To provide some useful context, thisdescription will first discuss a preferred embodiment of a computersystem and method for designing and creating integrated circuit chips.

[0015] By way of general background, chip designers often use electronicdesign automation (EDA) software tools to assist in the design process,and to allow simulation of a chip design prior to prototyping orproduction. Chip design using EDA software tools generally involves aniterative process whereby the chip design is gradually perfected.Typically, the chip designer builds up a circuit by inputtinginformation at a computer workstation generally having high qualitygraphics capability so as to display portions of the circuit design asneeded. A top-down design methodology is commonly employed usinghardware description languages (HDLs), such as Verilog® or VHDL, forexample, by which the designer creates an integrated circuit byhierarchically defining functional components of the circuit, and thendecomposing each component into smaller and smaller components.

[0016] Two of the primary types of components used in integratedcircuits are datapaths and control logic. Control logic, typicallyrandom logic, is used to control the operations of datapaths. Datapathareas of the circuit perform functional operations, such as mathematicalor other operations.

[0017] The various components of an integrated circuit are initiallydefined by their functional operations and relevant inputs and outputs.The designer may also provide basic organizational information about theplacement of components in the circuit using floorplanning tools. Duringthese design states, the designer generally structures the circuit usingconsiderable hierarchical information, and has typically providedsubstantial regularity in the design.

[0018] From the HDL or other high level description; the actual logiccell implementation is typically determined by logic synthesis, whichconverts the functional description of the circuit into a specificcircuit implementation. The logic cells are then “placed” (i.e., givenspecific coordinate locations in the circuit layout) and “routed” (i.e.,wired or connected together according to the designer's circuitdefinitions). The placement and routing software routines generallyaccept as their input a flattened netlist that has been generated by thelogic synthesis process. This flattened netlist identifies the specificlogic cell instances from a target standard cell library, and describesthe specific cell-to-cell connectivity. In addition, the method andsystem described herein may be used with a full customized design,wherein the transistor cells are fully customized by the designer.

[0019] Further explanation of a particular chip design process, withemphasis on placement and routing of datapaths, is set forth, forexample, in U.S. Pat. No. 5,838,583, hereby incorporated by reference asif set forth fully herein. Various embodiments as described hereinrelate in particular to the task of placing logic cells to arrive at acircuit layout.

[0020]FIG. 1 is a diagram of a computer system that may be used inconnection with various embodiments of the invention as describedherein. As shown in FIG. 1, a computer system 100 includes a computer110 connected to a display 191 and various input-output devices 192. Thecomputer 110 may comprise one or more processors (not shown), as well asworking memory (e.g., RAM) in an amount sufficient to satisfy the speedand processing requirements of the system. The computer 110 maycomprise, for example, a SPARC™ workstation commercially available fromSun Microsystems, Inc., or any other suitable computer.

[0021] The computer 110 contains stored program code including, in oneembodiment, a datapath floorplanner 120, a datapath placer 130 and arouting space estimator 140. The datapath flooplanner 120 provides forthe definition of datapath functions, datapath regions, and constraintson these for the purpose of interactive floorplanning operations by thecircuit designer, and the control of placement operations of thedatapath placer 130. The datapath placer 130 determines the placement ofdatapath functions within datapath regions, and the placement of logiccell instances within each datapath function, according to theconstraints defined by the circuit designer. The routing space estimator140 estimates routing space used for routing the datapath functions,given the placement of such functions by the datapath placer 130.

[0022] In support of the above-mentioned system components, a chipfloorplanner 150, global/detail router 160, standard cell placer 170,logic synthesizer 180, and HDL editor 190 may be usefully employed.Operation of the chip floorplanner 150, global/detail router 160,standard cell placer 170, logic synthesizer 180, and HDL editor 190 isconventional, as the design of these components is well known in the artof electronic design automation. Commercially available examples ofthese system components are Preview™, Cell3™, QPlace™, Synergy™, andVerilog®, respectively.

[0023] The computer 110 is preferably coupled to a mass storage device(e.g., magnetic disk or cartridge storage) providing a layout database195 with which the foregoing system components interface. The layoutdatabase 195 may be implemented using the EDIF database standard. Thecomputer 110 may also comprise or be connected to mass storagecontaining one or more component libraries (not shown) specifyingfeatures of electrical components available for use in circuit designs.

[0024] Referring now to FIG. 2, there is shown a schematic illustrationof a simplified integrated circuit 200 that may be represented byvirtual circuit design data stored in the layout database 195. Inactual, more realistic integrated circuit designs, the integratedcircuit 200 would be far more complicated. However, FIG. 2 is useful forpurposes of illustration. As shown therein, the integrated circuit 200comprises of a plurality of control regions 201, datapath regions 203,and memory 205. The various control regions 201, datapath regions 203and memory 205 are interconnected with databuses 207 generally spanningmultiple bits. Each datapath region 203 may comprise a plurality ofdatapath functions 209. A datapath function 209 may utilize some or allof the bits available from the databus 207. A datapath function 209 maycomprise a plurality of cell instances 215 which enable some form ofsignal or logic transformation of the data passed by the databus 207.The cell instance 215 within a datapath function 209 generally operateson the data carried on the datapath function 209.

[0025] As represented in the schema of the layout database 195, theintegrated circuit 200 is comprised of a plurality of instances and aplurality of nets. A net interconnects a number of instances, byassociating pins on each of the instances.

[0026]FIG. 3 is a diagram of a general process flow for a circuitdesign, illustrating some of the various levels of circuit abstractionas described above. As illustrated in FIG. 3, a register transfer logic(RTL) file 301 in the form of an HDL file or other high level functionaldescription undergoes a compile process 303, which typically includessome form of logic synthesis, and converts the functional description ofthe circuit into a specific circuit implementation which may be storedin the form of a netlist file 304. As part of the compile process 303, acomponent library 306 is generally referenced, which stores informationconcerning what types of design components are available, and thecharacteristics of those design components which are needed in order todetermine their functional connectivity. At this process stage, someattempt may be made at circuit optimization in order to minimize thenumber of components used in the circuit design. The netlist file 304,as previously noted, generally identifies the specific logic cellinstances from a target standard cell library, and describes thespecific cell-to-cell connectivity.

[0027] By application of a physical design process 309 shown in FIG. 3,the logic cells of the netlist file 304 are then placed and routed,resulting in a layout file 310. The component library 306 is utilized inthis process stage in order to obtain information concerning the sizesof gates and other components that may be present in the netlist file304.

[0028] From the layout file 310, a verification process 312 may be run,as further illustrated in FIG. 3, resulting in a mask file 315 in, forexample, a GDSII or CIF format. The mask file 315 may be provided to afoundry, and contains enough information to allow the foundry tomanufacture an actual integrated circuit therefrom.

[0029] According to the preferred embodiments as described herein, thephysical design process 309 includes a process to efficiently layout acircuit design in part by transistor folding in a manner so as to takeadvantage of the different row lengths in the integrated circuit 200.Preferably, the netlist file 304 which identifies the specific logiccell instances from a target standard cell library (e.g., componentlibrary 316) or from the full custom designed transistor cells and whichdescribes the specific cell-to-cell connectivity, is used as an input tothe process. The resulting output from the process is a layout file 310containing an efficient component layout for the integrated circuit 200,including folded transistors.

[0030] Transistor folding techniques described herein may be implementedas a computer program on the computer system 100 described previouslyfor integrated circuit chip design. In addition, some or all of themethods steps performed in the present invention may be implemented ashardware (e.g., using a programmable logic device), or a combination ofhardware and software. Additionally, some or all of the method steps maybe implemented using a computer usable/readable medium that is usable bya processor to execute the inventive methods. The associated methods maybe partially or completely automated. The resulting layout file 310 fromthe disclosed processes may be used to create an integrated circuit chip200 with components arranged to achieve efficient spatial utilization.

[0031] In one embodiment as disclosed herein, for a circuit designhaving transistors laid out in rows, a method for area layout reductionincludes the steps of determining the maximum row length, determining aset of possible row lengths for each row, selecting a row length foreach row resulting in the most area reduction for that row, determininga minimum height after folding for each row, determining a set ofpossible new heights for each row, and selecting a new height for eachrow from the set of possible new heights, the new height being above therow's minimum height but below the row's current height, such that thearea of the layout is reduced. Selection of the new height for each rowmay involve an iterative process wherein each possible new height istested and the resulting savings in area calculated. Once the new heightis selected, transistors in the given row are folded to accommodate thenew height.

[0032]FIGS. 4a and 4 b illustrate a basic physical design process 309 inwhich a transistor device 401 a is folded to achieve a more efficientcomponent layout. FIG. 4a depicts a transistor device 401 a having aheight W and comprising a source area S, gate area G, and drain area D.In FIG. 4a, transistor device 401 a is shown to have a minimum spacebetween the contact and diffusion l_(cd), a length of the contact l_(c),and a minimum space between the contact and poly-silicon area l_(cp). Asshown in FIG. 4a, the transistor device 401 a has been placed under highcongestion area 402. In the example depicted in FIG. 4a, transistordevice 401 a may represent the tallest transistor device placed in therow. Disposed above transistor 401 a are regions of high congestion area402 and low congestion area 403. Areas 402 and 403 may representadditional transistor elements or their respective routing layers whichmay cause electrical interference if placed too closely to transistordevice 401 a. Areas of high congestion (402) may contain a large numberof transistors or routing elements whereas areas of low congestion maycontain fewer to no elements, which cause electrical interference upontransistor 401 a. FIG. 4a also depicts an area to the right oftransistor device 401 a, directly beneath low congestion area 403. Asthis area contains no transistor device cells, prevents efficientutilization of the IC chip area is not achieved.

[0033] As the distance between diffusion areas of the transistor device401 a and the high congestion area 402 decreases, the probabilityparasitic electrical effects affecting the performance of the transistordevice 401 a increases. In addition, it may be the case that as thedistance between diffusion areas of the transistor device 401 a and thehigh congestion area 402 decreases, completion of the IC design is notpossible. This is because the routing between rows on a layout may notbe placed in the limited space between diffusion area and congestionarea. A minimum distance K must be reserved between rows to allow forrouting between rows. By increasing the minimum distance between rowsthe probability of performance degradation of transistor device 401 adecreases. Alternatively, a transistor device may be folded to decreasethe height requirement and the entire total chip area of the IC isdecreased. Thus, the reserved distance K between rows is maintained andthe total chip area is decreased.

[0034]FIG. 4b illustrates the same transistor device 401 b after it hasundergone a re-configuration of its geometry. As shown in FIG. 4b,transistor device 401 b retains the same l_(cd), l_(c), l_(cp)dimensions so that no additional parasitic effects occur as a result ofthe folding technique. Additionally the electrical contacts andperformance of transistor device 401 b provide the same results astransistor 401 a. However, as shown in FIG. 4b, the distance between thediffusion area of transistor device 401 b to the high congestion area402 increases by ⅔ W. Thus, the performance of the circuit may bedramatically improved and less likely to be subject to parasiticeffects. As a result, both areas 402 and 403 may subsequently be loweredon the actual physical layout of the IC without degrading theperformance of the IC. Thus, the total chip area of the IC may be moreefficiently utilized.

[0035] Next, the impact transistor folding has on the transistorperformance is discussed. Referring again to FIGS. 4a and 4 b, the mainconcern with transistor folding is whether the performance of thetransistor device after folding is better, worse than or the same as theperformance before the folding. The main factors that affect theperformance of the transistor in the layout view are the parasiticparameters, such AS (area of source), AD (area of drain), PS (peripheryof source), and PD (periphery of drain). These parasitic parameters willaffect the parasitic computation of the transistor and result in thedifferent delays of the transistor. Because of the symmetry of thesource and drain, the analysis of AD and PD are the same as AS and PS.Thus, only an analysis of AS and PS is performed. Before the folding, AScan be calculated as:

AS _(before) =W(l _(cd) +l _(c) +l _(cp))  (1)

[0036] where W is the width of the transistor. The value of l_(cd) isthe minimum space between the contact and the diffusion. l_(c) is thelength of the contact and l_(p) is the minimum space between the contactand the poly region. After the folding, the source S has been split astwo sources connected by a local wire, as shown in FIG. 4b. The new AScan be calculated as:

AS _(after)=⅓W(l _(cd) +l _(c) +l _(cp))+1/3W(l _(cp) +l _(c) +l_(cp))  (2)

[0037] Comparing AS_(after) with AS_(before):

AS _(before) −AS _(after)=⅓W(2l _(cd) +l _(c))  (3)

[0038] In an embodiment, the value of AS_(before)−AS_(after) is alwaysgreater than 0, which means the parasitic AS is reduced after folding.The smaller AS improves the transistor performance in terms of speed.

[0039] Next, the PS analysis is performed. Before the foldingPS_(before) is:

PS _(before)=2(W+l _(cd) +i _(c) +l _(cp))  (4)

[0040] After folding, PS_(after) is:

PS _(after)=2(⅓W+l _(cd) +l _(c) +l _(cp)+1/3W+l _(cp) +l _(c) +l_(cp))  (5)

[0041] Comparing PS_(after) with PS_(before):

PS _(before) −PS _(after)=2(⅓W+l _(cd) −l _(cp))  (6)

[0042] The value of PS_(before)−PS_(after) is greater than 0 in manycases. Therefore, in many cases, folding the transistor also reduces theparasitic parameter PS.

[0043] Transistor folding further improves the IC performance bybenefiting the routing between the various transistor devicesincorporated into the overall IC. When a transistor device is folded,two regions on the IC layout will be affected. In FIGS. 4a and 4 b,areas 402 and 403 are shown as the two areas affected by transistordevice folding. Areas 402 and 403 may contain either an area of highcongestion or low congestion. While in FIGS. 4a and 4 b, area 402 isdepicted as high congestion area and area 403 is depicted as lowcongestion area, statistically there are four combinations of areas 402and 403 that may occur. The benefits of transistor folding may affectthe overall performance in a variety of ways depending upon theconfiguration of the surrounding transistor devices.

[0044] Case 1: Area 402 is a high congestion area for routing, area 403is a less congested area. After folding, there will be approximately ⅔Wextra space for the routing. The wires for connecting the source anddrain can either use that space to connect the first source and drainterminals on the left side or use area 403 to connect the first sourceand drain terminals on the right side. Either way can reduce the burdenof the high congestion area 402.

[0045] Case 2: Area 402 is a high congestion area, area 403 is also ahigh congestion area. After transistor folding, these congestion areaswill be alleviated by using the extra space ⅔W provided to them forrouting after the transistor folding.

[0046] Case 3: Area 402 is a less congested area, area 403 is also aless congested area. The transistor folding impact on the routing maynot be significant, since ample area for routing is provided between thetransistor device and areas 402 and 403 both before and after transistorfolding.

[0047] Case 4: Area 402 is a less congested area, area 403 is a highcongestion area. Since adequate space is available for routing wiresbefore the transistor folding, the connecting wires for the source anddrain can go from the area 402. Thus, in this case, the transistorfolding impact on the routing may not be significant.

[0048] Overall, from the above four cases, it can be seen thattransistor folding can benefit routing. In many cases, it alleviatesovercrowding of certain areas upon the IC layout. Thus, transistorfolding continues to improve the performance of each individualtransistor device.

[0049] While it has been shown above that several electricalcharacteristics of the resulting folded transistor device are improved,the introduction of additional wires to connect the folded source anddrain terminals may slightly degrade the performance of the transistordevice 401 b. Referring to FIGS. 4a and 4 b, the resulting source anddrain terminals of folded transistor 401 b are separated from oneanother after the folding procedure and may require an additional lengthof wire to re-connect the terminals. The additional length of wire isintroduced to the connecting wire for S is approximately 21_(c)+4l_(cp)+2l_(p) (the distance between the two source terminals infolded transistor 401 b). l_(p) is the poly wire width. Before folding,the local wire length for the source terminals S is W. After folding,the local wire length for S is

S=⅓W+2l _(c)+4l _(cp)+2l _(p)  (7)

[0050] Therefore, whether the wire becomes longer or shorter isdetermined by the difference between ⅔W and 2l_(c)+4l_(cp)+2l_(p). If ⅔Wis greater than 2l_(c)+4l_(cp)+2l_(p), then the wire becomes shorterafter the folding and the performance of the transistor will be better.Otherwise, the wire becomes longer and the performance of the translatormay be deteriorated. Despite the potential for a slight degradation inIC performance due to an increased length of local wire connecting thevarious folded source and drain terminals, it can be seen thattransistor folding not only re-configures the geometry of a transistordevice, but may also help to improve transistor performance.

[0051] The preferred method described herein seeks to utilize transistorfolding at the layout stage to achieve the minimum chip area for anentire IC. A chip area consists of both area occupied by the transistordevices and the area occupied by the necessary routing area.

[0052] Due to design constraints the area occupied by transistor deviceswithin an IC will utilize a minimal required area. Thus, in oneembodiment the calculation of transistor area is:

Area_(transistors)=τrowheight_(i)*maxrowlength  (8)

rowheight_(i)=maxW_(ji subject to W) _(ji)≧MINSIZE  (9)

[0053] where rowheight_(i) is the height of the ith row. W_(ji) is thewidth of the jth transistor in row i. Maxrowlength is the longest row'slength of the layout. It includes the diffusion gap and space betweenthe transistors in the same row for routing. MINSIZE is the minimumtransistor size. For simplicity, MINSIZE is used instead of usingPMINSIZE and NMINSIZE separately. PMINSIZE represents the minimum sizeof pfet transistors and NMINMIZE represents the minimum size of nfettransistors.

[0054] Optimization of the actual physical layout of the IC canadditionally involve minimizing the area occupied by the routing. Byreducing the routing area, the total chip area of the IC may be reduced.In the designing of the layout that will undergo transistor folding, avertical space K is already reserved for the routing between rows.However, the folding procedures for the transistors change the shapes ofthe transistors and may further affect the routing. The estimation ofthe routing area changed due to the transistor fold is difficult if thetransistor folding procedure is executed before the layout. However, inthe various embodiments, the estimation is facilitated, because avertical space K has already been reserved for the routing and anychanges for the existing wire due to the transistor folding can beassumed as the local changes. Thus, in this embodiment the calculationof the routing area for each row is:

Area_(routing)=(K+S _(ji)(n))*maxrowlength  (10)

[0055] where K is defined above as the space reserved for the routingbetween rows. S_(ji)(n) is the additional space introduced locally bythe transistor j at row i with ii folds due to folding.

[0056] The following will describe the manner in which S_(ji)(n) iscalculated in an embodiment of the invention. In the example illustratedin FIGS. 4a and 4 b, the transistor device 401 a represents a transistordevice that is incorporated in a new custom IC design before folding.Transistor device 401 b depicts transistor device 401 a folded into 3transistors. It can be seen that only two local wires (two tracks) areneeded for connecting the same source (S) terminals and drain (D)terminals. For other folding numbers, such as 5,7,9 . . . folds, onlytwo local wires are needed for connecting the same source/drainterminals. Therefore, a method of an embodiment sets the routingoverhead S_(ji)(n) as a constant. Setting Q=K+S_(ji)(nn), Q is then alsoset as a constant.

[0057] By adding up the transistor area and routing area. The objectivefunction becomes:

minimize(Σrowheigt_(i) +Q)*maxrowlength)  (11)

[0058] Thus, the present method determines how to fold each transistorto reduce the area of physical layout by taking the advantage ofdifferent rows' lengths.

[0059] From Equation 11, the total chip area of the IC may be reduced byreducing the heights of the rows and finding the optimal maxrowlengthwhich can give freedom for each row to fold the transistors in the rowto achieve the maximum area reduction.

[0060] According to Equation 11, the area is determined by two items,maxrowlength and Σrowheight_(i). Therefore, the system and method of theembodiment optimizes the overall chip area in two-phases. Phase Idetermines the maxrowlength. Phase II determines row height. By doingthis, the method and systems solves the two-dimensional transistorfolding problem.

[0061] Phase I: Finding Maxrowlength In this phase, the maxrowlength iscalculated. From the layout after transistor sizing, the initialmaxrowlength_(init) is identified Each row can become the longest rowafter folding the transistors in that row. The length of row j can berepresented as:

rowlength_(j) =a ₁ l ₁ +a ₂ l ₂ + . . . +a _(i) l _(i) + . . . a _(n) l_(n)  (12)

[0062] Where l_(i) is the length of transistor i in the row and includescontacts etc. a₁, a₂ . . . , a_(n) are integers. a_(i) indicates howmany splits transistor i has. The range of a_(i) can be represented by:$\begin{matrix}{1 \leq a_{i} < \frac{{LENGTHLIMIT} - {{initial}\quad {{row}'}s\quad {length}}}{l_{i}}} & (13)\end{matrix}$

[0063] where LENGTHLIMIT is the limit of the row length, which is userdefined. The number of all possible lengths of row j is: $\begin{matrix}{\prod\limits_{i = 1}^{m}\quad \left( \frac{{LENGTHLIMIT} - {{initial}\quad {{row}'}s\quad {length}}}{l_{i}} \right)} & (14)\end{matrix}$

[0064] where in is the numbers of transistor in row j. Among allpossible lengths, the bestrowlength_(j) for row j can be found toachieve the best area reduction due to the folding. Bestrowlength_(j)can be longer than maxrowlength_(initial) as long as:

bestrowlength_(j)×(H−ΔH)≦max rowlength_(init) ×H  (15)

[0065] where H is the height of row j. ΔH is the amount of the height ofthe row that will be decreased due to the folding.

[0066] After Phase I, the method builds a set (S) of bestrowlength_(j)by choosing the bestrowlength_(j) which is greater thanmaxrowlength_(init). Each value in the set (S) is a potentialmaxrowlength. Because it may not known which one results in the maximumtotal area reduction of the layout, each will be used in Phase II tofind the maximum area reduction.

[0067] Phase II: Folding Transistors

[0068] In this phase, the area reduction for folding transistors basedon each maxrowlength is calculated and the maximum area reduction as thefinal result is selected. In order to reduce the computation, minh isfirst calculated for each row. minh is the possible minimum height ofthe row after folding. The transistor device heights that are greaterthan minh are possible solutions. The following equation calculates theminh. $\begin{matrix}{{\sum{\left( \frac{h_{i}}{\min \quad h} \right) \times l_{i}}} \leq {\max \quad {rowlength}}} & (16)\end{matrix}$

[0069] Because one goal is to minimize minh, the above equation becomesΣ(h_(i)/minh)*l_(i)=maxrowlength The idea of introducing minh can beused to reduce the computation.

[0070] Referring to FIGS. 5 and 6, the method is described by way of anexample. FIG. 5 illustrates a sample IC layout. Known transistor devices501, 502, 503, and 504 are placed onto the IC substrate 500 in row 1.Transistor device 505 is placed onto the IC substrate in row 2. Thelengths of transistor devices 501, 502, 503, 504, and 505 are 4, 4, 6,4, and 40, respectively. The heights are 12, 4, 8, 15, and 4,respectively. Suppose transistor device 505 is a macro cell whosegeometry cannot be modified. In Phase I, the method finds the initialmaxrowlength is 40 (the length of transistor device 505 in row 2). Forrow 2, the method finds the possible maxrowlength, it is still 40. InPhase II, the method first calculates the minh of row 1:

((12/minh)*4)+((4/minh)*4)+((8/minh)*6)+((15/minh)*4)=40  (17)

[0071] Solving for minh, the equation yields minh=4.3. Keeping in mindthat the minimum height possible is 4.3, the method then calculates thepossible heights of each transistor in the row as it is folded.Transistor device 501, for example, begins with an initial height of 12.Folding transistor 501 into 2 segments yields a new height of 6. Foldingtransistor 501 into 3 segments yields a height of 4. This is not apossible solution for the height of row 1 as it does not meet the minhof 4.3. Referring to transistor 502, the initial height of thetransistor is already denoted to be 4, thus no further folding oftransistor 502 is needed. Transistor 503 is initially designed with aheight of 8. Folding transistor 503 into 2 segments yields a transistorheight of 4. Transistor 504 is designed with an initial height of 15.Folding this transistor into 2 segments yields a transistor with aheight of 7.5 (rounded to be 8). Folding transistor 504 into 3 segmentsyields a transistor with a height of 5. Any further folding oftransistor 504 will not yield a possible height solution as it will belower than the calculated minh. Thus, the possible height solutions forrow 1 are 8, 6, or 5.

[0072] Since a transistor may only be folded an integral number ofkinds, as for solving. Solving for the length of row 1 for a height of8, the length is found to be approximately 26. Solving for a height of6, the length is approximated to be 36. Setting the height of row 1 to 5provides a row length of 40. If the height of row 1 is set any lowerthan 5, the length of row 1 exceeds the maxrowlength of 40. At thispoint each transistor is folded such that their heights do not exceedthe row height of 5.

[0073]FIG. 6 illustrates the final optimized physical layout of the IC.By folding the transistor 501, 502, 503, and 504 additional space isallotted between rows. This space can be used either to incorporateadditional transistor devices within the IC substrate or may provideadditional spacing to counteract any potential parasitic effect.

[0074] The method described herein may be performed by the computersystem described earlier in FIG. 1. The computer 110 contains a storedprogram code to implement the steps of the optimization method. Thepossible stored code for Phase I may be as follows: for each rowfor(each transistor in the row) { find.possible.fold.size (w₁, W₂, . . .w_(n)) } for(each set of possible height) { merge( ), merging allpossible transistor heights. } for(each possible transistor height) {find the bestrowlength_(j) }

[0075] In line 3 of the above code, w_(n)=h_(i)/n; where w_(n)≧MINSIZE,and h_(i) is the height of transistor i. Since any transistor can befolded only by multiple-integrals, the possible heights of transistor iare represented by the equation h_(i)/n, where (h_(i)/n≧MINSIZE). Lines2-4, of the exemplary code, calculate all the possible heights of eachtransistor in the row. Next, lines 5-7 merge all calculated possibleheights of the transistors into a set of monotonously decreasingpossible row heights. Finally, lines 8-9 compute area reduction and findthe maximum area reduction. The bestrowlength_(j) is also calculatedfrom lines 8-9.

[0076] The possible stored code for Phase II may be as follows: for eachmaxrowlength for each row find the minimum row's height (minh) based onthe current maxrowlength (maxrowlength). for each height from thehighest possible height to minimum row's height estimate the foldingeffect, if (new rowlength < maxrowlength) continue; if (new rowlength ≧maxrowlength) find the new row's length and break; end end end find themaximum area reduction. folding transistors.

[0077] The complexity of lines 24 of the exemplary stored code for PhaseI may be represented by the function O(n), where n is the number of thetransistors in the circuit. Thus, the amount of time to process andperform the function denoted by lines 2-4 of the stored code is directlya function of the number of transistor in the circuit. Furthermore, thecomplexity of lines 5 and 6 are also represented by the same functionO(n). In line 3 of the stored code, a set of sorted possible heights isgenerated for each transistor. The time needed to generate the set is alinear function of the transistors in the set. Likewise, the complexityof lines 8-9 is also represented by the function O(n). Thus, the timeneeded to calculate the maxrowlength is linearly related to the numberof transistors in the circuit.

[0078] In Phase II, the number of maxrowlength may be represented as Q,and the number of rows may be represented by m. Thus, the total numberof possible heights of each row is p*n/Q, where p is the maximum numberof possible heights of each transistor. Therefore, the total complexitywill be O(Q*m*p*n/Q). Simplifying the function, the resulting complexityfunction is represented as O(m*p*n). In the usual case, m and p arebounded. Therefore, the complexity of Phase II of the method can berepresented by the function O(n). In the worst case, m=n, the complexityof the algorithm takes on the form of O(n²). As the situation where eachrow has only one transistor (i.e., m=n). On average, the computationcomplexity of the method is O(n). Thus, the method described herein canbe said to have a computational complexity of O(n). Therefore, the timeneeded to complete the optimization method described herein is linearlyrelated to the total number of transistors in the circuit.

[0079] A system and method of practical transistor folding has beendescribed herein which can be used in the high performance IC physicaldesign flow. The system and method takes the advantage of differentrows' lengths and introduces the possible minimum row's height (minh)which reduces the computation. The experimental results show theefficacy of the algorithm.

[0080] While preferred embodiments of the invention have been describedherein, many variations are possible which remain within the concept andscope of the invention. Such variations would become clear to oneskilled in the art upon perusal of the description of the embodimentsset forth herein.

What is claimed:
 1. A method of optimizing an integrated circuit layoutcomprising the steps of: a) calculating a first total chip area of afirst proposed layout, the first proposed layout representing transistordevices placed on the integrated circuit layout; b) determining apossible rowlength value that produces a modified total chip area lessthan the first total chip area; c) calculating a minimum row heightcorresponding to the determined possible rowlength value; d) iterativelyvarying the height value of a row, wherein the height is greater thanthe minimum row height; e) calculating a value of the modified totalchip area using the determined possible rowlength value and iterativelyvaried height value; f) iteratively repeating steps b) through e) todetermine an optimal total chip area; and g) generating an optimalintegrated circuit layout.
 2. The method of claim 1, wherein the step ofcalculating a minimum row height comprises dividing the sum of areas oftransistor devices placed in the first proposed layout by the determinedpossible rowlength.
 3. The method of claim 1, wherein the step ofcalculating a first total chip area comprises multiplying a maximumrowlength of the first proposed layout by a first total height of thefirst proposed layout.
 4. The method of claim 1, wherein the step ofcalculating a modified total chip area comprises calculating a totalrowheight value by adding a constant Q to the iteratively varied heightvalue, wherein the constant Q represents a sum of a reserved space forrouting between rows and an additional space that is introduced locallyto each transistor as a result of transistor folding; calculating asecond total height by adding the total rowheight of each row; andmultiplying the second total height by the determined possible rowlengthvalue.
 5. The method of claim 1, further comprising the step of foldingeach transistor device to achieve the varied height value used for eachrow of the optimal integrated circuit layout.
 6. A system for optimizingan integrated circuit layout comprising: a) means for calculating afirst total chip area of a first proposed layout, the first proposedlayout representing transistor devices placed on the integrated circuitlayout; b) means for determining a possible rowlength value thatproduces a modified total chip area less than the first total chip area;c) means for calculating a minimum row height corresponding to thedetermined possible rowlength value; d) means for iteratively varyingthe height value of a row, wherein the height is greater than theminimum row height; e) means for calculating a value of the modifiedtotal chip area using the determined possible rowlength value anditeratively varied height value; f) means for iteratively repeatingsteps b) through e) to determine an optimal total chip area; and g)means for generating an optimal integrated circuit layout.
 7. The systemof claim 6, wherein the means for calculating a minimum row heightcomprises a means for dividing the sum of areas of transistor devicesplaced in the first proposed layout by the determined possiblerowlength.
 8. The system of claim 6, wherein the means for calculating afirst total chip area comprises a means for multiplying a maximumrowlength of the first proposed layout by a first total height of thefirst proposed layout.
 9. The system of claim 6, wherein the means forcalculating a modified total chip area comprises: means for calculatinga total rowheight value by adding a constant Q to the iteratively variedheight value, wherein the constant Q represents a sum of a reservedspace for routing between rows and an additional space that isintroduced locally to each transistor as a result of transistor folding;means for calculating a second total height by adding the totalrowheight of each row; and means for multiplying the second total heightby the determined possible rowlength value.
 10. The system of claim 6,further comprising a means for folding each transistor device to achievethe varied height value used for each row of the optimal integratedcircuit layout.
 11. A system for optimizing an integrated circuit layoutcomprising: a layout database, wherein the layout database stores knownlayouts for integrated circuit functions; a computer processor forcalculating a first total chip area, a modified total chip area, and aminimum height of a row corresponding to a determined possiblerowlength, the computer processor is further capable of determining thepossible rowlength such that the modified total chip area is less thanthe first total chip area; a row height generator capable of generatingiteratively variable row heights greater than the calculated minimum rowheight; and a display capable of generating an image of the optimalintegrated circuit layout.
 12. A method for area layout reductioncomprising the steps of: placing transistor devices in rows of a firstlayout design, calculating an area value for the first layout design;determining a maximum row length of the first layout design; determininga set of possible row lengths for each row of the first layout design;selecting a row length for each row resulting in a maximum areareduction for that row; determining a minimum height after folding foreach row to achieve the selected rowlength; determining a set ofpossible new heights for each row; iteratively selecting a new heightfor each row from the set of possible new heights, the new height beingabove the row's minimum height but below the row's current height, suchthat the area of the first layout design is reduced; and folding thetransistor devices in each row to conform with the selected new height.13. The method of claim 12, wherein the step of determining the minimumrow height comprises dividing the sum of areas of transistor devicesplaced in the first proposed layout by the determined possiblerowlength.
 14. The method of claim 12, wherein the step of calculatingthe area value comprises multiplying a maximum rowlength of the firstlayout design by a first total height of the first layout design.
 15. Asystem for optimizing an integrated circuit layout comprising: a meansfor placing transistor devices in rows of a first layout design, a meansfor calculating an area value for the first layout design; a means fordetermining a maximum row length of the first layout design; a means fordetermining a set of possible row lengths for each row of the firstlayout design; a means for selecting a row length for each row resultingin a maximum area reduction for that row; a means for determining aminimum height after folding for each row to achieve the selectedrowlength; a means for determining a set of possible new heights foreach row; a means for iteratively selecting a new height for each rowfrom the set of possible new heights, the new height being above therow's minimum height but below the row's current height, such that thearea of the first layout design is reduced; and a means for folding thetransistor devices in each row to conform with the selected new height.16. A method of designing an integrated circuit layout comprising thesteps of: placing a plurality of cells on a first design layout; andfolding two or more of the plurality of cells of the first designlayout.
 17. The method of claim 16, wherein each of the plurality ofcells comprises one or more transistor devices.
 18. The method of claim16, further comprising the step of determining an optimal height andlength parameter for rows of the first design layout.
 19. The method ofclaim 18, wherein the step of determining the optimal length parametercomprises proposing a possible row length values for each row of thefirst design layout such that a total chip area is reduced and storingsaid possible row length values as a first set in memory.
 20. The methodof claim 19, further comprising calculating a minimum height of each rowcorresponding to each possible row length value stored in the set,generating a second set of possible row height values wherein eachpossible row height is greater than the calculated minimum height, andstoring the second set in memory.
 21. The method of claim 20, furthercomprising iteratively calculating total chip area values using eachpossible row length value stored in the first set and each possible rowheight value stored in the second set.
 22. The method of claim 21,further comprising the step of determining the optimal total chip areafrom the iteratively calculated total chip area values.
 23. A system fordesigning an integrated circuit layout comprising: means for placingtransistor devices on a first design layout; and means for foldingtransistor devices in a plurality of cells of the first design layout.24. A method of designing an integrated circuit layout comprising thesteps of: placing a plurality of cells on a first design layout; foldingtwo or more of the plurality of cells in multiple rows of the firstdesign layout; and determining resulting electrical effects between rowsof the first design layout due to folding.
 25. The method of claim 23,wherein each of the plurality of cells comprises one or more transistordevices.
 26. The method of claim 23, wherein each row of the multiplerows comprises one or more cells.
 27. The method of claim 23, furthercomprising the step of determining an optimal height and lengthparameter for rows of the first design layout.
 28. The method of claim27, wherein the step of determining the optimal length parametercomprises proposing a possible row length values for each row of thefirst design layout such that a total chip area is reduced and storingsaid possible row length values as a first set in memory.
 29. The methodof claim 28, further comprising calculating a minimum height of each rowcorresponding to each possible row length value stored in the set,generating a second set of possible row height values wherein eachpossible row height is greater than the calculated minimum height, andstoring the second set in memory.
 30. The method of claim 29, furthercomprising iteratively calculating total chip area values using eachpossible row length value stored in the first set and each possible rowheight value stored in the second set.
 31. The method of claim 30,further comprising the step of determining the optimal total chip areafrom the iteratively calculated total chip area values.
 32. A system fordesigning an integrated circuit layout comprising: means for placing aplurality of cells on a first design layout; means for folding two ormore of the plurality of cells in multiple rows of the first designlayout; and means for determining resulting electrical effects betweenrows of the first design layout due to folding.
 33. A method ofdesigning an integrated circuit layout comprising the steps of: placingtransistor devices on a first design layout; and folding transistordevices in each row of the first design layout to provide an optimaltotal chip area for the integrated circuit layout based on a globalanalysis of the total chip area reduction.
 34. The method of claim 33,further comprising the step of determining an optimal height and lengthparameter for rows of the first design layout.
 35. The method of claim34, wherein the step of determining the optimal length parametercomprises proposing a possible row length values for each row of thefirst design layout such that a total chip area is reduced and storingsaid possible row length values as a first set in memory.
 36. The methodof claim 35, further comprising calculating a minimum height of each rowcorresponding to each possible row length value stored in the set,generating a second set of possible row height values wherein eachpossible row height is greater than the calculated minimum height, andstoring the second set in memory.
 37. The method of claim 36, furthercomprising iteratively calculating total chip area values using eachpossible row length value stored in the first set and each possible rowheight value stored in the second set.
 38. The method of claim 37,further comprising the step of determining the optimal total chip areafrom the iteratively calculated total chip area values.
 39. A system fordesigning an integrated circuit layout comprising: means for placingtransistor devices on a first design layout; and means for foldingtransistor devices in each row of the first design layout to provide anoptimal total chip area for the integrated circuit layout based on aglobal analysis of the total chip area reduction.
 40. A method ofdesigning an integrated circuit layout comprising the steps of: placinga number of transistor devices on a first design layout; determiningoptimal height and length parameters for each row of the first layoutdesign, wherein step of determining the optimal height and lengthparameters in each row occurs in a time that is linearly related to thenumber of transistor devices placed on the first design layout; andfolding transistor devices in each row of the first design layout toconform with the optimal height and length parameters.
 41. The method ofclaim 40, further wherein the step of determining the optimal lengthparameter comprises proposing a possible row length values for each rowof the first design layout such that a total chip area is reduced andstoring said possible row length values as a first set in memory. 42.The method of claim 41, further comprising calculating a minimum heightof each row corresponding to each possible row length value stored inthe set, generating a second set of possible row height values whereineach possible row height is greater than the calculated minimum height,and storing the second set in memory.
 43. The method of claim 42,further comprising iteratively calculating total chip area values usingeach possible row length value stored in the first set and each possiblerow height value stored in the second set.
 44. The method of claim 43,further comprising the step of determining the optimal total chip areafrom the iteratively calculated total chip area values.
 45. A system fordesigning an integrated circuit layout comprising: means for placing anumber of transistor devices on a first design layout; means fordetermining optimal height and length parameters for each row of thefirst layout design, wherein step of determining the optimal height andlength parameters in each row occurs in a time that is linearly relatedto the number of transistor devices placed on the first design layout;and means for folding transistor devices in each row of the first designlayout to conform with the optimal height and length parameters.
 46. Asystem for designing an integrated circuit layout comprising: means forplacing and routing transistor devices on a first design layout; andmeans for folding transistor devices of the first design layout based onanalysis of both transistor area and routing area.
 47. The system ofclaim 46, further comprising means for determining an optimal height andlength parameter for rows of the first design layout.
 48. The system ofclaim 47, wherein determining the optimal length parameter comprisesproposing a possible row length values for each row of the first designlayout such that the total chip are is reduced and storing said possiblerow length values as a first set in memory.
 49. The system of claim 48,further comprising means for calculating a minimum height of each rowcorresponding to each possible row length value stored in the set,generating a second set of possible row height values wherein eachpossible row height is greater than the calculated minimum height, andstoring the second set in memory.
 50. The system of claim 49, furthermeans for comprising iteratively calculating total chip area valuesusing each possible row length value stored in the first set and eachpossible row height value stored in the second set.
 51. The system ofclaim 50, further comprising determining the optimal total chip areafrom the iteratively calculated total chip area values.
 52. A method fordesigning an integrated circuit layout comprising the steps of: placingand routing transistor devices on a first design layout; and foldingtransistor devices of the first design layout based on analysis of bothtransistor area and routing area.
 53. The method of claim 52, furthercomprising the step of determining an optimal height and lengthparameter for rows of the first design layout.
 54. The method of claim53, wherein the step of determining the optimal length parametercomprises proposing a possible row length values for each row of thefirst design layout such that the total chip are is reduced and storingsaid possible row length values as a first set in memory.
 55. The methodof claim 54, further comprising calculating a minimum height of each rowcorresponding to each possible row length value stored in the set,generating a second set of possible row height values wherein eachpossible row height is greater than the calculated minimum height, andstoring the second set in memory.
 56. The method of claim 55, furthercomprising iteratively calculating total chip area values using eachpossible row length value stored in the first set and each possible rowheight value stored in the second set.
 57. The method of claim 56,further comprising the step of determining the optimal total chip areafrom the iteratively calculated total chip area values.